1·When the switching voltage is at or below 1.5v, connecting an external resistive divider to this input will lower the UVLO threshold.
当开关电压等于或低于1.5 V的，连接一个外部电阻分压器来此输入UVLO阈值将降低。
2·The easiest way to accomplish this is to apply a potential across the entire tube and tap the dynode voltages off a voltage divider, as shown in Figure 4-13.
做到这一点最容易的方法是给整个光电倍增管的两端加上一个电压，然后从一个分压器的各个抽头取得供给各个倍增管电极的电压，如图4 - 13所示。
3·Connected to the other input of the error amp is the midpoint of a voltage divider. We'll come back to this later.
连接误差放大器另一个输入点的是一个电压分压器的中点电压。稍后我们再来讨论。
4·It gives the principle and method of design that coaxial capacitive voltage divider by the invar alloy.
给出了以因瓦合金为材料的同轴电容分压器的原理和设计方法。
5·Divider, coaxial line, trigger, signal processing, data acquisition, acquisition control and waveform analysis software is included in the device.
该装置包括分压器、同轴电缆、触发电路、信号处理、数据采集、控制和分析软件。
1·The theory and method of precedent cellular arrays divider by means of FPGA are introduced.
介绍了用FPGA实现先行进位单元阵列除法器的原理及方法。
2·In order to improve the speed of division, a novel algorithm of radix-16 high speed divider and its ASIC implementation are presented.
为提高除法计算的速度，提出了新的基-16算法的高速除法器算法，并以专用集成电路设计方法实现。
3·This paper reports a technique used lor improving the stability of the laser probe consisting of an acoustooptic modulator, an analogue divider and an auto-lock-in amplifier.
本文介绍了一种用声光调制器、模拟除法器和自动锁相放大器来改进激光探针测试系统稳定性的方法。