1·My question is, how do I know what the input CLK frequency should be?
我的问题是，我怎么知道输入时钟频率应该是多少？
2·I've read the datasheet but can't find any reference to specifying an input CLK frequency.
我读过的数据表，但找不到任何参考指定一个输入时钟频率。
3·The fiducial clk and reset source of each part is same , and the information transmitted form part to part is on line.
在设计中整个系统采用了一个基准时钟源和同步源，并且各部分间的信号传输采用了有线的方式。
4·Data is read serially by the Driver IC on the input CLK rising edge once the STB input line goes low.
数据读取连续的驱动ic的输入时钟的上升沿一旦机顶盒输入线变低。
5·In these two modes the data and CLK pins should not be clocked to reduce noise in the captured pressure or temperature data.
在这两个数据和时钟引脚不应时钟频率为减少捕获的压力和温度数据的噪音模式。